11419 E. Gamble Ln
Scottsdale, AZ 85262
ph: (480) 518 - 4570
dgupta
Our Track record
includes many industry firsts. At semiconductor majors like Motorola and Intel we developed a suite of technologies that enabled the introduction of traditionally expensive flip chip interconnection to low - cost microprocessors for PCs. These flip chip technologies included the development of electro -plated solder bumping process that replaced the earlier and costlier standard of evaporated bump process ( C - 4 ), the first machine vision - assisted robotic tool for assembly of flip chips, thus allowing great improvements in throughput compared to earlier technologies, the first organic substrate for microprocessors, design and start - up of the first high yield fab for high volume manufacturing of these substrates, worlds first flip chipped gallium arsenide power amplifiers which allowed dramatic cost reduction and allowed their introduction in mobile phones, electoplated copper column bumps for microproecssors, low cost electroless nickel column bumps and more.
We apply a wide spectrum of in - depth expertise in materials, process and design in a coherent manner to your Advanced Packaging problems so as to quickly create for you effective and robust solutions, be it in root cause analyses for a failing package or a whole Wafer Bumping or Robotic Assembly Line ready to run....
Take advantage of our demonstrated trouble - shooting skills in the procssing area. For technologies already in production reduce your line - down time. Intel did so ! With our turnkey engineering a much smaller semiconductor house was able to start their Wafer Bumping Line from scratch and ramp production in just 8 months.
APSTL llc is led by Dr. Dev Gupta, an industry veteran with both R&D and Management experience at Motorola and Intel. He is recognized by the Electronic Packaging community as an expert and has received awrads from IEEE, IMAPS etc. Dr. Gupta also frequently teaches Advanced Packaging coursee at IEEE Conferences and Workshops and was a Member of the IEEE Interconnects Commitee. He is backed at APSTL by a team of experts in Materials Characterization and Package Design.
11419 E. Gamble Ln
Scottsdale, AZ 85262
ph: (480) 518 - 4570
dgupta